A multi-core processor uses system on chip (SOC) technology to integrate multiple general-purpose CPUs and functional components onto a single chip, where the CPUs communicate with each other and with the functional components through high-speed buses. The use of high-speed buses breaks through the performance bottleneck in communication between CPUs and CPUs/components in a traditional multi-CPU system, thus guaranteeing system performance.
The cores of a multi-core system can concurrently access a critical resource (also referred to as a shared resource). To avoid data confusion caused by multiple cores concurrently accessing the same critical node in a critical resource, a core must poll whether the critical node it is attempting to access is locked. If the critical node is locked, it waits; if the critical node is not locked, it locks the critical node first and then accesses the critical node, for example, to delete the critical node. Such a lock-and-act mechanism prevents access errors that can be caused when multiple cores access the same critical node at the same time.
Unfortunately, while preventing errors caused by concurrent accesses of cores to the same critical node, the lock-and-act mechanism of multi-core systems increases system overheads and thus reduces critical resource accessing efficiency.